1. Technical Field
The present disclosure relates to a semiconductor device and to a method of fabricating the same and, more particularly, to a semiconductor device that includes a dual gate and a method of fabricating the same.
2. Description of the Related Art
With regard to semiconductor devices, the recent trend has been toward higher performance and higher speed. In particular, in the case of a semiconductor device that include both an n-channel metal-oxide semiconductor (NMOS) transistor and a p-channel metal-oxide semiconductor (PMOS) transistor, efforts have been made to optimize the performance of the transistor according to the respective transistor type.
The above-mentioned efforts include changing the structures of gates of the NMOS transistor and the PMOS transistor or using a high-k dielectric layer that has dielectricity higher than that of a silicon oxide layer as a gate insulating layer, thereby making technological progress.
For example, in the case where the gate includes a polysilicon layer, to avoid the gate depletion, the gate has an MIPS (metal-inserted polysilicon) structure. However, with the gate that has the MIPS structure, the work function may be changed due to the inserted metal layer, and thus as a result, the threshold voltage Vth may be changed. Consequently, difficulties may result in that physical properties of the semiconductor device may be reduced.
Meanwhile, in the case where the gate including the metal layer instead of the polysilicon layer is used, the depletion of the gate may be prevented. However, in the case of metal, it may be very difficult to control the work function due to impurities unlike with the polysilicon layer. Accordingly, in the case where metal having a single work function is used, it may be difficult to desirably control the threshold voltage of the NMOS transistor and the PMOS transistor. In addition, in the case where the NMOS and the PMOS are formed of metals having different work functions, it may be difficult to perform the integration.